Recently, there is a trend for obtaining size reduction and high integration in bipolar LSI (Large Scale Integration). Accordingly, in transistors that are used in bipolar LSI, the size reduction of transistors is increasing with the use of size reduction processes such as the photolithography technique, the dry-etching technique and so on, in addition to the technique of oxide isolation used in conventional structures. Additionally there are many proposals for transistors which are of new structures and made by using new techniques of oxide isolation.
In a SICOST which is recited in IEEE Transactions on Electron Devices "Self-Aligned Transistor with Sidewall Base Electrode" by T. Nakamura et al., Vol. ED-29, No. 4, Apr. 1982, P. 596-600, it is disclosed that it is possible to reduce a collector-base junction capacity C.sub.TC and an emitter-base junction capacity C.sub.TE to a great extent. This is done by constructing a collector-base junction and an emitter-base junction only in both of the main surface portions of an active base region and, not constructing any junctions for an inactive base region, thereby enhancing the performance of bipolar LSIs by using SICOSTs to a great extent.
FIG. 1 is a cross-sectional view showing a prior art SICOST.
In FIG. 1, the numeral 1 designates a p.sup.- type silicon substrate 1, and an n.sup.+ type embedded collector layer 2 is provided in a part of the main surface region of the silicon substrate 1. An n.sup.- type collector region 3, a p.sup.+ active base region 4, and an n.sup.+ type emitter region 5, each of the three regions being composed of a single crystalline silicon layer, overlap one after another in the mentioned order on a part of the surface of the embedded collector layer 2, thereby constituting an npn transistor of n.sup.- p.sup.+ n.sup.+ structure. An n.sup.+ type collector leading region 6, composed of a single crystalline silicon layer, is provided on a part of the n.sup.+ type embedded collector layer 2 apart from the collector region 3. A p.sup.+ type channel cut region 7 is provided on the whole main surface of the p.sup.- type silicon substrate 1 except for the part where the n.sup.+ type embedded collector layer 2 is provided. A SiO.sub.2 film 8 is provided over the surface of the n.sup.+ type embedded collector layer 2 and the surface of the p.sup.+ type channel cut region 7, and it surrounds the n.sup.- type collector region 3, the p.sup.+ type active base region 4, the n.sup.+ type emitter region 5, and the n.sup.+ type collector leading region 6. A p.sup.+ type inactive polycrystalline base region 9, composed of a p.sup.+ type polycrystalline silicon layer, is provided embedded in the SiO.sub.2 film 8, and one end of the base region 9 is provided in contact with and surrounding a given part of the side wall of the p.sup.+ type active base region 4. A base electrode 10, composed of an aluminum (Al) film, is provided in contact with the other end of the p.sup.+ type inactive polycrystalline base region 9 through a contact hole produced in the part of the SiO.sub.2 film 8 which part is located on the other end of the base region 9. An emitter electrode 11, composed of an Al film, is provided in contact with the n.sup.+ type emitter region 5. A collector electrode 12, composed of an Al film, is provided in contact with the n.sup.+ type collector leading region 6.
In this prior art device, the n.sup.- type collector region 3, the p.sup.+ type active base region 4, and the n.sup.+ type emitter region 5 overlap one after another in the mentioned order on the n.sup.+ type embedded collector layer 2. Accordingly, a collector-base junction and an emitter-base junction are constituted only in the junction between the p.sup.+ type active base region 4 and the n.sup.- type collector region 3 and in the junction between the p.sup.+ type active base region 4 and the n.sup.+ type emitter region 5 respectively, and no pn junctions are created between the p.sup.+ type inactive base region 9 and the n.sup.- type collector region 3 and between the inactive base region 9 and the n.sup.+ type emitter region 5. This is an alteration of the conventional structure of a transistor where the base region is constructed in a part of the surface portion of the collector region and the emitter region is constructed in a part of the surface portion of the base region. This means that the above-described transistor is constructed by removing the emitter-base junction that is made between the side wall of the emitter region and the inactive base region, which is the portion of the base region except for the active base region under the emitter region also, collector-base junction that exists between the inactive base region and the collector region.
The above described transistor it is capable of reducing the collector-base junction capacity C.sub.TC and the emitter-base junction capacity C.sub.TE to a greater extent than transistors of a conventional structure. The capability of reducing the emitter-base junction capacity C.sub.TE becomes more important as fineness of the structure advances. For example, when the area of the emitter region is 0.5 .mu.m square and the diffusion depth of impurities is 0.4 .mu.m, the area of the bottom of the emitter region becomes 0.25 .mu.m.sup.2 (=0.5.times.0.5), and the area of the side wall thereof becomes 0.8 .mu.m.sup.2 (=0.5.times.4.times.0.4). The ratio of the emitter-base junction capacity C.sub.TE of the prior art device of FIG. 1 relative to the emitter-base junction capacity C.sub.TE of the transistors of conventional structure is 1/4 because it is a ratio of the area of the bottom of the emitter region that is in contact with the base region (which is 0.25 .mu.m.sup.2) relative to the area which is obtained by adding the area of the side wall of the emitter region that is in contact with the inactive base region (which is 0.8 .mu.m.sup.2) to the above mentioned area of the bottom of the emitter region (0.25 .mu.m.sup.2), which is about 1 .mu.m.sup.2 (=0.25+0.8).
It is possible to make the ratio of the junction capacitances C.sub.TE of both transistors smaller than the above mentioned ratio of capacitances by making the impurity density of the surface portion of the emitter region higher than that of the bottom portion, thereby enhancing the performance of the bipolar LSI using this prior art device.
The advantages of this prior art device are described in the following concrete example.
Generally, in an emitter coupled logic (which is abbreviated as ECL) which is constituted by a current switching transistor and an emitter follower transistor, a propagation delay time t.sub.pd is represented by the following formula. EQU t.sub.pd =0.7r.sub.bb '.C.sub.IN +0.7R.sub.C (C.sub.TS +C.sub.R)+0.5 .times.[0.7.times.(R.sub.C +r.sub.bb ')C.sub.INEF +0.5.DELTA.Vo.C.sub.EF /I.sub.EF] (I)
where
R.sub.C =.DELTA.V.sub.o /I.sub.CS PA1 C.sub.IN =2C.sub.TC +0.5C.sub.TE +I.sub.SC /(2f.sub.T..DELTA.V.sub.IN) . . . equivalent input capacity (Unit: F) PA1 C.sub.TS . . . collector-substrate junction capacity (Unit: F) PA1 r.sub.bb ' . . . base resistance (Unit: .OMEGA.) PA1 .DELTA.V.sub.IN . . . input logical amplitude (Unit: V) PA1 .DELTA.V.sub.o . . . output logical amplitude (Unit: V) PA1 C.sub.R . . . parasitic capacity of collector load (Unit: F) PA1 L.sub.CS . . . switching current (Unit: A) PA1 and the "EF" . . . represents that the value is related to the emitter follower transistor PA1 C.sub.EF =C.sub.IN (where it is presumed that the emitter follower transistor drives a gate of the next stage only) PA1 I.sub.EF =I.sub.CS =300 (.mu.A), C.sub.R =0.014 (pF) PA1 r.sub.bb '=200 (.OMEGA.) PA1 .DELTA.V.sub.o =.DELTA.V.sub.in =0.6 (V), f.sub.T =5 (GHz) PA1 t.sub.pd =2.820C.sub.TC +0.705C.sub.TE +1.400C.sub.TS +0.042 (nsec) . . . [II]
When a prior art SICOST is used in constituting a current switching transistor and an emitter follower transistor of an ECL, the current switching transistor and the emitter follower transistor have the same structure and the above formula [I] is revised to formula [II] shown below. The following constants are presumed considering fineness of structure, thereby making it easy to understand the ratio caused by only the junction capacities.
where the unit of the capacities C.sub.TC, C.sub.TE and C.sub.TS is pF.
Although the capability of reducing the junction capacities C.sub.TC and C.sub.TE contributes largely to shortening the propagation delay time t.sub.pd in an ECL using this prior art device, it is necessary to minimize the collector-substrate junction capacity C.sub.TS in order to bring about a greater reduction of the delay time. However, it is not easy to minimize the collector-substrate junction capacity C.sub.TS caused by the pn junction between the n.sup.+ type embedded collector layer 2 and the p.sup.+ type silicon substrate 1 and between the embedded collector layer 2 and the p.sup.+ type channel cut region 7 because the n.sup.- type collector region 3 and the n.sup.+ type collector leading region 6 must be provided on the surface of the embedded collector layer 2 thereby resulting in the incapability of reducing the dimension of the n.sup.+ type embedded collector layer 2.